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PRELIMINARY
CYU01M16ZFC MoBL3TM
16-Mbit (1M x 16) Pseudo Static RAM
Features
* Wide voltage range: 1.7V-1.95V * Access Time: 70 ns * Ultra-low active power -- Typical active current: 3 mA @ f = 1 MHz -- Typical active current: 18 mA @ f = fmax * Ultra low standby power * 16-word Page Mode * Automatic power-down when deselected * CMOS for optimum speed/power * Deep Sleep Mode * Offered in a Lead-Free 48-ball BGA Package * Operating Temperature: -40C to +85C can be put into standby mode when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE LOW) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enables (CE LOW) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a complete description of read and write modes. Deep Sleep Mode is enabled by driving ZZ LOW. See the Truth Table for a complete description of Read, Write, and Deep Sleep mode.
Functional Description[1]
The CYU01M16ZFC is a high-performance CMOS Pseudo Static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device
Logic Block Diagram
A8 A9 A10
DATA IN DRIVERS
A11 A12 A13 A14 A15 A16 A17 A18 A19
ROW DECODER
1M x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE OE
A6 A5 A4 A3 A2 A1 A0
A7
CE
Power-Down Circuit
BHE BLE
BLE
ZZ Refresh/Power-down Circuit
CE
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05604 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 16, 2006
PRELIMINARY
Pin Configuration[2, 3]
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15
A18
CYU01M16ZFC MoBL3TM
2 OE BHE I/O10 I/O11
Top View 4 3 A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10
VFBGA
5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
6 ZZ I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
I/O12 NC I/O13 A19 A8 A14 A12 A9
Product Portfolio[4]
Power Dissipation Product CYU01M16ZFC Min. 1.7 VCC Range (V) Typ.[4] 1.8 Max. 1.95 70 Speed (ns) Operating ICC (mA) f = 1MHz Typ.[4] 3 Max. 5 f = fmax Typ.[4] 18 Max. 25 Standby ISB2 (A) Typ.[4] 55 Max. 70
Low-Power Modes
At power-up, all four sections of the die are activated and the PSRAM enters into its default state of full memory size and refresh space. This device provides four different Low-Power Modes. 1. Reduced Memory Size Operation 2. Partial Array Refresh 3. Deep Sleep Mode 4. Temperature Controlled Refresh Reduced Memory Size Operation In this mode, the 16 Mb PSRAM can be operated as a 12-Mbit, 8-Mbit or a 4-Mbit memory block. Please refer to "Variable Address Space Register (VAR)" on page 4 for the protocol to turn on/off sections of the memory. The device remains in RMS mode until changes to the Variable Address Space register are made to revert back to a complete 16-Mbit PSRAM. Partial Array Refresh The Partial Array Refresh mode allows customers to turn off sections of the memory block in the Stand-by mode (with ZZ
tied low) to reduce standby current. In this mode the PSRAM will only refresh certain portions of the memory in the Stand-By Mode, as configured by the user through the settings in the Variable Address Register. Once ZZ returns high in this mode, the PSRAM goes back to operating in full address refresh. Please refer to "Variable Address Space Register (VAR)" on page 4 for the protocol to turn off sections of the memory in Stand-By mode. If the VAR register is not updated after the power up, the PSRAM will be in its default state. In the default state the whole memory array will be refreshed in the Stand-By Mode. The 16-Mbit MoBL3 is divided into four 4-Mbit sections allowing certain sections to be active (i.e., refreshed). Deep Sleep Mode In this mode, the data integrity in the PSRAM is not guaranteed. This mode can be used to lower the power consumption of the PSRAM in an application. This mode can be enabled and disabled through VAR similar to the RMS and PAR mode. Deep Sleep Mode is activated by driving ZZ LOW. The device stays in the deep sleep mode until ZZ is driven HIGH.
Notes: 2. Ball H6, E3 can be used to upgrade to 32M and 64M density respectively. 3. NC "no connect" - not connected internally to the die. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. Tested initially and after any design changes that may affect the parameter.
Document #: 38-05604 Rev. *F
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PRELIMINARY
Variable Address Mode Register (VAR) Update[5, 6]
tWC ADDRESS CE tAW t BW BHE / BLE t SA t WE t ZZ
tZZMIN
ZZWE PWE
CYU01M16ZFC MoBL3TM
Lower-order address (A0-A4) Low Power Modes
tHA
Deep Sleep Mode--Entry/Exit [7]
t ZZMIN ZZ Deep Sleep Mode t CE t
CDR
R
VAR Update and Deep Sleep Mode Timing[5, 6]
Parameter tZZWE tCDR tR[7] tZZMIN Description ZZ LOW to Write Start Chip deselect to ZZ LOW Operation Recovery Time (Deep Sleep Mode only) Deep Sleep Mode Time 0 200 8 Min. Max. 1 Unit s ns s s
Notes: 5. OE and the data pins are in a don't care state while the device is in variable address mode. 6. All other timing parameters are as shown in the data sheets. 7. tR applies only in the deep sleep mode.
Document #: 38-05604 Rev. *F
Page 3 of 14
PRELIMINARY
Variable Address Space Register (VAR)
I
CYU01M16ZFC MoBL3TM
A19-A5
A4
A3
A2
A1
A0
Memory Array Selection 00 - 16M(Default) 01 - 12M 10 - 8M 11 - 4M Top/Bottom Half Selection Reserved 0 - Bottom (Default) 1 - Top Array On/Off on ZZ ZZ Enable/Disable 0 - PAR Mode (Default) 0 - Deep Sleep Enabled (Default) 1 - RMS Mode 1 - Deep Sleep Disabled
Variable Address Space--Address Patterns
Partial Array Refresh Mode (A3 = 0, A4 = 1) A2 0 0 0 1 1 1 0 0 0 0 1 1 1 1 A1, A0 11 10 01 11 10 01 11 10 01 00 11 10 01 00 Refresh Section 1/4th of the array 1/2th of the array 3/4th of the array 1/4th of the array 1/2th of the array 3/4th of the array Address 00000h - 3FFFFh (A19 = A18 = 0) 00000h - 7FFFFh (A19 = 0) 00000h - BFFFFh (A19:A18 not equal to 1 1) C0000h - FFFFFh (A19 = A18= 1) 80000h - FFFFFh (A19 = 1) 40000h - FFFFFh (A19:A18 not equal to 0 0) Reduced Memory Size Mode (A3 = 1, A4 = 1) 1/4th of the array 1/2th of the array 3/4th of the array Full array 1/4th of 3/4
h of
Size 256K x 16 512K x 16 768K x 16 256K x 16 512K x16 786K x16 256K x 16 512K x 16 768K x 16 1M x 16 256K x 16 512K x 16 768K x 16 1M x 16
Density 4M 8M 12M 4M 8M 12M 4M 8M 12M 16M 4M 8M 12M 16M
00000h - 3FFFFh (A19 = A18 = 0) 00000h - 7FFFFh (A19 = 0) 00000h - BFFFFh (A19:A18 not equal to 1 1) 00000h - FFFFFh (Default) C0000h - FFFFFh (A19 = A18 = 1) 80000h - FFFFFh (A19 = 1) 40000h - FFFFFh (A19:A18 not equal to 0 0) 00000h - FFFFFh (Default)
the array the array
1/2th of the array Full array
Page Mode
This device can be operated in a page read mode. This is accomplished by initiating a normal read of the device. In order to operate the device in page mode, the upper order address bits should be fixed for four-word page access operation, all address bits except for A1 and A0 should be fixed until the page access is completed. For an eight-word page access, all address bits, except for A2, A1, and A0, Page Mode Feature Page Length Page Read Corresponding Addresses Page Read Start Address Page Direction
should be fixed. For a sixteen-word page mode all address bits, except for A3, A2, A1, and A0, should be fixed. The supported page lengths are four, eight, and sixteen words. Random page read is supported for all three four, eight, and sixteen-word page read options. Therefore, any address can be used as the starting address. Please, refer to the table below for an overview of the page read modes. 8-Word Mode 8 words A2, A1, A0 Don't Care Don't Care 16-Word Mode 16 words A3, A2, A1, A0 Don't Care Don't Care
4-Word Mode 4 words A1, A0 Don't Care Don't Care
Document #: 38-05604 Rev. *F
Page 4 of 14
PRELIMINARY
Power-up Characteristics
The initialization sequence is shown in the figure below. Chip Select (CE) should be HIGH for at least 200 s after VCC has reached a stable value. No access must be attempted during this period of 200 s.The state of ZZ has to be high (H) for the duration of power-up.
Stable Power VCC
CYU01M16ZFC MoBL3TM
Logic (HIGH) ZZ First Access
Tpu CE
Parameter Tpu
Description Chip Enable Low After Stable VCC
Min. 200
Typ.
Max.
Unit s
Document #: 38-05604 Rev. *F
Page 5 of 14
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential .-0.2V to VCCMAX + 0.3V DC Voltage Applied to Outputs in High Z State[8, 9, 10] ......................-0.2V to VCCMAX + 0.3V
CYU01M16ZFC MoBL3TM
DC Input Voltage[8, 9, 10] .................. -0.2V to VCCMAX + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... > 200 mA Operating Temperature (TA)
Device
Range
VCC
CYU01M16ZFC Industrial -40C to +85C 1.7V to 1.95V
DC Electrical Characteristics Over the Operating Range [8, 9, 10]
CYU01M16ZFC-70 Parameter VCC VOH VOL VIH VIL IIX IOZ ICC Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current VCC Operating Supply Current IOH = -0.1 mA VCC= 1.7V to 1.95V IOL = 0.1 mA VCC= 1.7V to 1.95V 1.7V < VCC < 1.95 VCC= 1.7V to 1.95V GND < VIN < VCC f = fMAX = 1/tRC f = 1 MHz ISB1 Automatic CE Power-Down Current -- CMOS Inputs Automatic CE Power-Down Current -- CMOS Inputs Deep Sleep Current CE > VCC - 0.2V, VI > VCC - 0.2V, VIN < 0.2V f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = 1.95V, ZZ >= VCC - 0.2V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = VCCMAX ZZ>= VCC - 0.2V VCC = VCCMAX, ZZ < 0.2V, CE = HIGH or BHE and BLE = HIGH VCC= VCCmax IOUT = 0 mA CMOS levels 0.8 * VCC -0.2 -1 -1 18 Test Conditions Min. 1.7 VCC - 0.2 0.2 VCC + 0.3 0.2 * VCC +1 +1 25 Typ.[4] 1.8 Max. 1.95 Unit V V V V V A A mA
Output Leakage Current GND < VOUT < VCC
3 55
5 70
mA A
ISB2
55
70
A
IZZ
10
A
Capacitance[11]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 8 8 Unit pF pF
Notes: 8. VIL(MIN) = -0.5V for pulse durations less than 20 ns. 9. VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns. 10. Overshoot and undershoot specifications are characterized and are not 100% tested. 11. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05604 Rev. *F
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PRELIMINARY
Thermal Resistance[11]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA / JESD51.
CYU01M16ZFC MoBL3TM
V FBGA 56 11 Unit C/W C/W
AC Test Loads and Waveforms
VCC OUTPUT R1 VCC GND 30 pF INCLUDING JIG AND SCOPE R2 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Rise Time = 1 V/ns Equivalent to:
THEVENIN EQUIVALENT RTH OUTPUT VTH Unit V
Parameters R1 R2 RTH VTH
1.8V (VCC) 14000 14000 7000 0.90
Document #: 38-05604 Rev. *F
Page 7 of 14
PRELIMINARY
Switching Characteristics Over the Operating Range[12, 13, 14, 15, 18]
70 ns Parameter Read Cycle tRC [17] tCD tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE Page Read Cycle tPC tPA Write Cycle[15] tWC tSCE tCD tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Chip Deselect Time CE, BLE/BHE High Pulse Time Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to WE HIGH to High-Z[13, 14, 16] Low-Z[13, 14, 16] 10 70 60 15 60 0 0 50 60 25 0 Page Mode Read Cycle Time Page Mode Address Access 35 Read Cycle Time Chip Deselect Time CE, BLE/BHE High Pulse Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z
[13, 14, 16] [13, 14, 16]
CYU01M16ZFC MoBL3TM
Description
Min. 70 15
Max. 40000
Unit ns ns
70 5 70 35 5 25 10 25 70 5 25 40000 35 40000
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z CE HIGH to High
CE LOW to Low Z[13, 14, 16] Z[13, 14, 16] Z[13, 14, 16] BLE/BHE LOW to Data Valid BLE/BHE LOW to Low BLE/BHE HIGH to High Z[13, 14, 16]
25
ns ns
Notes: 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 13. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWEfor any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (1.8V) 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 16. High-Z and Low-Z parameters are characterized and are not 100% tested. 17. If invalid address signals shorter than min. tRC are continuously repeated for 40 s, the device needs a normal read timing (tRC) or needs to enter standby state at least once in every 40 s. 18. In order to achieve 70ns performance, the read access must be CE controlled. That is, the addresses must be stable prior to CE going active.
Document #: 38-05604 Rev. *F
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PRELIMINARY
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[20, 21] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA
CYU01M16ZFC MoBL3TM
DATA VALID
Read Cycle 2 (OE Controlled)[19, 21]
ADDRESS tRC
CE
tCD tACE
tHZCE
BHE/BLE
tLZBE
OE
tDBE
tHZBE tHZOE HIGH IMPEDANCE ICC ISB
DATA OUT VCC SUPPLY CURRENT
tLZOE HIGH IMPEDANCE tLZCE
tDOE DATA VALID
50%
50%
Notes: 19. Whenever CE, BHE/BLE are taken inactive, they must remain inactive for a minimum of 15 ns 20. Device is continuously selected. OE, CE = VIL. 21. WE is HIGH for Read Cycle.
Document #: 38-05604 Rev. *F
Page 9 of 14
PRELIMINARY
Switching Waveforms (continued)
Page Read Cycle (ZZ = WE = VIH, 16 word access)[17, 21]
t RC
A4-A19
CYU01M16ZFC MoBL3TM
tAA
A0-A3
tOHA
t PC CE t ACE t tHZBE
OE
DOE
t HZCE BHE/BLE tDBE t LZCE DATA OUT High Z t PAA
DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID
Write Cycle 1 (WE Controlled)[15, 16, 19, 22, 23]
t WC
ADDRESS tSCE
CE
tCD
tSA
WE
tAW
tPWE
tHA
BHE/BLE
tBW
OE
tSD DATA I/O
DON'T CARE
tHD
VALID DATA tHZOE
Notes: 22. Data I/O is high-impedance if OE > VIH. 23. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05604 Rev. *F
Page 10 of 14
PRELIMINARY
Switching Waveforms (continued)
Write Cycle 2 (CE Controlled)[15, 16, 19, 22, 23]
CYU01M16ZFC MoBL3TM
t WC ADDRESS tSCE CE
tSA
tAW
tHA tPWE
WE tBW
BHE/BLE
OE t HZOE DATA I/O
DON'T CARE
tSD VALID DATA
tHD
Write Cycle 3 (WE Controlled, OE LOW)[ 19, 23] tWC ADDRESS tSCE
CE
BHE/BLE
tBW tAW tHA
tSA
WE
tPWE
tSD DATA I/O
DON'T CARE
tHD tLZWE
VALID DATA tHZWE
Document #: 38-05604 Rev. *F
Page 11 of 14
PRELIMINARY
Switching Waveforms (continued)
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[15, 19, 22, 23] tWC ADDRESS
CYU01M16ZFC MoBL3TM
CE tSCE tAW BHE/BLE tSA WE tBW tHA
tPWE tSD tHD
DATA I/O
DON'T CARE
VALID DATA
Truth Table[24, 25]
ZZ H H H H H H H H H H H H L L CE H X L L L L L L L L L L H H WE X X X H H H H H H L L L X X OE X X X L L L H H H X X X X X BHE X H H L H L L H L L H L H X BLE X H H L L H L L H L L H H X Inputs/Outputs High Z High Z High Z Data Out (I/O0-I/O15) Data Out (I/O0-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/O0-I/O15) Data In (I/O0-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0 -I/O7 in High Z Data in (A0-A4) High Z Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Read Read Read Output Disabled Output Disabled Output Disabled Write (Upper Byte and Lower Byte) Write (Lower Byte Only) Write (Upper Byte Only) Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Write (Variable Address Mode Active (ICC) Register) Deep Power-down / PAR Deep Sleep (IZZ) / Stand by
Notes: 24. H = Logic HIGH, L = Logic LOW, X = Don't Care. 25. During ZZ = L and CE = H, Mode depends on how the VAR is set up either in PAR or Deep Sleep Modes.
Document #: 38-05604 Rev. *F
Page 12 of 14
PRELIMINARY
Ordering Information
Speed (ns) 70 Ordering Code CYU01M16ZFCU-70BVXI Package Name BV48 Package Type
CYU01M16ZFC MoBL3TM
Operating Range Industrial
48-ball Fine Pitch VFBGA (6 mm x 8 mm x 1 mm) Lead-Free
Please contact your local Cypress Sales representative for availability of other parts.
Package Diagram
48-Lead VFBGA (6 x 8 x 1 mm) BV48
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
TOP VIEW
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85150-*D
SEATING PLANE 0.26 MAX. C 1.00 MAX
MoBL is a registered trademark and MoBL3 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05604 Rev. *F
Page 13 of 14
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
Document Title: CYU01M16ZFC MoBL3TM 16-Mbit (1M x 16) Pseudo Static RAM Document Number: 38-05604 REV. ** *A *B ECN NO. 278869 280850 314034 Issue Date See ECN See ECN See ECN Orig. of Change SYT REF PCI Description of Change New Data Sheet
CYU01M16ZFC MoBL3TM
Updated Ordering information to incorporate lead-free parts. Corrected Part Number Added Operating Range in Features Section Moved address lines A8 - A10 from Column decoder to Row decoder in the Logic Block Diagram Changed Pin Configuration Diagram Name from FBGA to VFBGA Added pin E3 in note #2 Modified description on Deep Sleep Mode Changed tZZWE description Changed JA and JC from 55 and 17 C/W to 56 and 11C/W respectively Modified Test Condition for IIX and IOZ Changed VCC(typ) to VCC in note # 12 Changed tOHA from 10 ns to 5 ns Changed tSCE, tAW and tBW from 45 to 50 ns Changed tRC and tWC from 6000 ns to 40000 ns Changed tPC and tPA from 15 ns to 20 ns Added Parameter tCD in AC Table and its corresponding footnote in Notes Section Changed R1 and R2 from 13500 and 10800 to 14000 Changed RTH from 6000 to 7000 Parameter tCD added in Read Cycle 2 and Write Cycle 1 Timing Diagrams Changed from Advance Information to Preliminary Modified Logic Block Diagram Modified description on Deep Sleep Mode Deleted Page Write in the Page Mode Feature Table Added CE, BHE and BLE in test conditions for IZZ in DC Table Modified condition in the third row of the Truth Table for ZZ Pin from X to H Changed tPC and tPA from 20 to 25 ns Replaced TBDs with appropriate values Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Removed 55 ns Speed Bin. Removed Reference to BHE/ BLE from DPD wave form on page # 3. Added ZZ in Power Up characteristics on page# 5. Added ISB1 specification in the DC characteristics table on page #6. Added test condition ZZ>= VCC-0.2V for ISB2 Updated the Truth Table for DPD / PAR and Write (Variable Address Mode Register) Modes. Changed TCD value to 15 ns from 5 ns on Read and Write Cycles Changed TPC and TPAA values to 35 ns from 25 ns Included "Chip Enable Access" footnote in AC Parameters Changed Isb2 value from 60A to 70A
*C
351780
See ECN
PCI
*D *E
386551 406266
See ECN See ECN
PCI NXR
*F
420604
See ECN
HRT
Document #: 38-05604 Rev. *F
Page 14 of 14

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